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| MAX 7000A (R) Includes MAX 7000AE Programmable Logic Device Data Sheet October 2002, ver. 4.3 Features... High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX(R)) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability - MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532 - EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532 Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71 Enhanced ISP features - Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices) - ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices) - Pull-up resistor on I/O pins during in-system programming Pin-compatible with the popular 5.0-V MAX 7000S devices High-density PLDs ranging from 600 to 10,000 usable gates Extended temperature range f For information on in-system programmable 5.0-V MAX 7000 or 2.5-V MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Altera Corporation DS-M7000A-4.3 1 MAX 7000A Programmable Logic Device Data Sheet Table 1. MAX 7000A Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz) EPM7032AE 600 32 2 36 4.5 2.9 2.5 3.0 227.3 EPM7064AE 1,250 64 4 68 4.5 2.8 2.5 3.1 222.2 EPM7128AE 2,500 128 8 100 5.0 3.3 2.5 3.4 192.3 EPM7256AE 5,000 256 16 164 5.5 3.9 2.5 3.5 172.4 EPM7512AE 10,000 512 32 212 7.5 5.6 3.0 4.7 116.3 ...and More Features 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM , and plastic J-lead chip carrier (PLCC) packages Supports hot-socketing in MAX 7000AE devices Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance PCI-compatible Bus-friendly architecture, including programmable slew-rate control Open-drain output option Programmable macrocell registers with individual clear, preset, clock, and clock enable controls Programmable power-up states for macrocell registers in MAX 7000AE devices Programmable power-saving mode for 50% or greater power reduction in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell Programmable security bit for protection of proprietary designs 6 to 10 pin- or logic-driven output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Fast input setup times provided by a dedicated path from I/O pin to macrocell registers Programmable output slew-rate control Programmable ground pins 2 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Software design support and automatic place-and-route provided by Altera's development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with Altera's Master Programming Unit (MPU), MasterBlasterTM serial/universal serial bus (USB) communications cable, ByteBlasterMVTM parallel port download cable, and BitBlasterTM serial download cable, as well as programming hardware from third-party manufacturers and any JamTM STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File- (.svf) capable in-circuit tester General Description MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2. Table 2. MAX 7000A Speed Grades Device -4 EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Speed Grade -5 -6 -7 v v v v v v v v v v v -10 v v v v v v v v v v -12 v v Altera Corporation 3 MAX 7000A Programmable Logic Device Data Sheet The MAX 7000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high-density integration of SSI, MSI, and LSI logic functions. It easily integrates multiple devices including PALs, GALs, and 22V10s devices. MAX 7000A devices are available in a wide range of packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA, PQFP, and TQFP packages. See Table 3 and Table 4. Table 3. MAX 7000A Maximum User I/O Pins Device 44-Pin PLCC 44-Pin TQFP Note (1) 49-Pin Ultra FineLine BGA (2) 41 68 68 84-Pin PLCC 100-Pin TQFP 100-Pin FineLine BGA (3) 68 84 84 84 EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE 36 36 36 36 68 84 84 84 84 Table 4. MAX 7000A Maximum User I/O Pins Device EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Notes to tables: (1) (2) Note (1) 256-Pin BGA 256-Pin FineLine BGA (3) 144-Pin TQFP 169-Pin Ultra 208-Pin PQFP FineLine BGA (2) 100 100 120 120 120 100 164 164 176 212 100 100 164 164 212 (3) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O pins become JTAG pins. All Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See "SameFrame Pin-Outs" on page 15 for more details. All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device migration is fully supported by Altera development tools. See "SameFrame Pin-Outs" on page 15 for more details. 4 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet MAX 7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. MAX 7000A devices contain from 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and highspeed parallel expander product terms, providing up to 32 product terms per macrocell. MAX 7000A devices provide programmable speed/power optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 7000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. The output drivers of all MAX 7000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 7000A devices to be used in mixed-voltage systems. MAX 7000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text--including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)--and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX-workstation-based EDA tools. The software runs on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations. f For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. Altera Corporation 5 MAX 7000A Programmable Logic Device Data Sheet Functional Description The MAX 7000A architecture includes the following elements: Logic array blocks (LABs) Macrocells Expander product terms (shareable and parallel) Programmable interconnect array I/O control blocks The MAX 7000A architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 7000A devices. 6 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 1. MAX 7000A Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 or 10 Output Enables (1) LAB A 36 36 6 or 10 Output Enables (1) LAB B 2 to 16 2 to 16 2 to 16 I/O 2 to 16 I/O Control Block Macrocells 1 to 16 16 Macrocells 17 to 32 2 to 16 I/O Control Block 2 to 16 I/O 16 6 2 to 16 2 to 16 2 to 16 6 LAB C PIA Macrocells 33 to 48 16 36 36 LAB D 2 to 16 2 to 16 I/O I/O Control Block 2 to 16 Macrocells 49 to 64 2 to 16 I/O Control Block 2 to 16 I/O 16 6 2 to 16 2 to 16 6 Note: (1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables. EPM7512AE devices have 10 output enables. Logic Array Blocks The MAX 7000A device architecture is based on the linking of high-performance LABs. LABs consist of 16-macrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells. Each LAB is fed by the following signals: 36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions Direct input paths from I/O pins to the registers that are used for fast setup times Altera Corporation 7 MAX 7000A Programmable Logic Device Data Sheet Macrocells MAX 7000A macrocells can be individually configured for either sequential or combinatorial logic operation. The macrocells consist of three functional blocks: the logic array, the product-term select matrix, and the programmable register. Figure 2 shows a MAX 7000A macrocell. Figure 2. MAX 7000A Macrocell LAB Local Array Global Clear Parallel Logic Expanders (from other macrocells) Global Clocks 2 From I/O pin Fast Input Select Programmable Register Register Bypass To I/O Control Block PRN D/T Q ProductTerm Select Matrix VCC Clock/ Enable Select ENA CLRN Clear Select Shared Logic Expanders 36 Signals from PIA 16 Expander Product Terms To PIA Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The product-term select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocell's register preset, clock, and clock enable control functions. Two kinds of expander product terms ("expanders") are available to supplement macrocell logic resources: Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells The Altera development system automatically optimizes product-term allocation according to the logic requirements of the design. 8 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes: Global clock signal. This mode achieves the fastest clock-to-output performance. Global clock signal enabled by an active-high clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins. Two global clock signals are available in MAX 7000A devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the product-term select matrix allocates product terms to control these operations. Although the product-term-driven preset and clear from the register are active high, active-low control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE device may be set to either a high or low state. This power-up state is specified at design entry. Upon power-up, each register in EPM7128A and EPM7256A devices are set to a low state. All MAX 7000A I/O pins have a fast input path to a macrocell register. This dedicated path allows a signal to bypass the PIA and combinatorial logic and be clocked to an input D flipflop with an extremely fast (as low as 2.5 ns) input setup time. Altera Corporation 9 MAX 7000A Programmable Logic Device Data Sheet Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, more complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources. However, the MAX 7000A architecture also offers both shareable and parallel expander product terms that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. Shareable Expanders Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. A small delay (tSEXP) is incurred when shareable expanders are used. Figure 3 shows how shareable expanders can feed multiple macrocells. Figure 3. MAX 7000A Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic 36 Signals from PIA 16 Shared Expanders 10 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. The compiler can allocate up to three sets of up to five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (tPEXP). For example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms, and the second set includes four product terms, increasing the total delay by 2 x tPEXP. Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lowernumbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of eight, the lowest-numbered macrocell can only lend parallel expanders, and the highest-numbered macrocell can only borrow them. Figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell. Altera Corporation 11 MAX 7000A Programmable Logic Device Data Sheet Figure 4. MAX 7000A Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. From Previous Macrocell Preset ProductTerm Select Matrix Clock Clear Macrocell ProductTerm Logic Preset ProductTerm Select Matrix Clock Clear Macrocell ProductTerm Logic 36 Signals from PIA 16 Shared Expanders To Next Macrocell Programmable Interconnect Array Logic is routed between LABs on the PIA. This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 7000A dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure 5 shows how the PIA signals are routed into the LAB. An EEPROM cell controls one input to a 2-input AND gate, which selects a PIA signal to drive into the LAB. 12 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 5. MAX 7000A PIA Routing To LAB PIA Signals While the routing delays of channel-based routing schemes in masked or FPGAs are cumulative, variable, and path-dependent, the MAX 7000A PIA has a predictable delay. The PIA makes a design's timing performance easy to predict. I/O Control Blocks The I/O control block allows each I/O pin to be individually configured for input, output, or bidirectional operation. All I/O pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or VCC. Figure 6 shows the I/O control block for MAX 7000A devices. The I/O control block has 6 or 10 global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins, or a subset of the I/O macrocells. Altera Corporation 13 MAX 7000A Programmable Logic Device Data Sheet Figure 6. I/O Control Block of MAX 7000A Devices 6 or 10 Global Output Enable Signals (1) PIA OE Select Multiplexer VCC To Other I/O Pins From Macrocell GND Open-Drain Output Slew-Rate Control Fast Input to Macrocell Register To PIA Note: (1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enable signals. EPM7512AE devices have 10 output enable signals. When the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the I/O pin can be used as a dedicated input. When the tri-state buffer control is connected to VCC, the output is enabled. The MAX 7000A architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic. 14 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet SameFrame Pin-Outs MAX 7000A devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the arrangement of balls on FineLine BGA packages such that the lower-ballcount packages form a subset of the higher-ball-count packages. SameFrame pin-outs provide the flexibility to migrate not only from device to device within the same package, but also from one package to another. A given printed circuit board (PCB) layout can support multiple device density/package combinations. For example, a single board layout can support a range of devices from an EPM7128AE device in a 100-pin FineLine BGA package to an EPM7512AE device in a 256-pin FineLine BGA package. The Altera design software provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The software generates pin-outs describing how to lay out a board to take advantage of this migration (see Figure 7). Figure 7. SameFrame Pin-Out Example Printed Circuit Board Designed for 256-Pin FineLine BGA Package 100-Pin FineLine BGA 256-Pin FineLine BGA 100-Pin FineLine BGA Package (Reduced I/O Count or Logic Requirements) 256-Pin FineLine BGA Package (Increased I/O Count or Logic Requirements) Altera Corporation 15 MAX 7000A Programmable Logic Device Data Sheet In-System Programmability MAX 7000A devices can be programmed in-system via an industrystandard 4-pin IEEE Std. 1149.1 (JTAG) interface. ISP offers quick, efficient iterations during design development and debugging cycles. The MAX 7000A architecture internally generates the high programming voltages required to program EEPROM cells, allowing in-system programming with only a single 3.3-V power supply. During in-system programming, the I/O pins are tri-stated and weakly pulled-up to eliminate board conflicts. The pull-up value is nominally 50 k. MAX 7000AE devices have an enhanced ISP algorithm for faster programming. These devices also offer an ISP_Done bit that provides safe operation when in-system programming is interrupted. This ISP_Done bit, which is the last bit programmed, prevents all I/O pins from driving until the bit is programmed. This feature is only available in EPM7032AE, EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices. ISP simplifies the manufacturing flow by allowing devices to be mounted on a PCB with standard pick-and-place equipment before they are programmed. MAX 7000A devices can be programmed by downloading the information via in-circuit testers, embedded processors, the Altera MasterBlaster serial/USB communications cable, ByteBlasterMV parallel port download cable, and BitBlaster serial download cable. Programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., QFP packages) due to device handling. MAX 7000A devices can be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. In-system programming can be accomplished with either an adaptive or constant algorithm. An adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. A constant algorithm uses a predefined (non-adaptive) programming sequence that does not take advantage of adaptive algorithm programming time improvements. Some in-circuit testers cannot program using an adaptive algorithm. Therefore, a constant algorithm must be used. MAX 7000AE devices can be programmed with either an adaptive or constant (non-adaptive) algorithm. EPM7128A and EPM7256A device can only be programmed with an adaptive algorithm; users programming these two devices on platforms that cannot use an adaptive algorithm should use EPM7128AE and EPM7256AE devices. The Jam Standard Test and Programming Language (STAPL), JEDEC standard JESD 71, can be used to program MAX 7000A devices with incircuit testers, PCs, or embedded processors. 16 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet f For more information on using the Jam STAPL language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor) and Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded Processor). ISP circuitry in MAX 7000AE devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Programming with External Hardware f MAX 7000A devices can be programmed on Windows-based PCs with an Altera Logic Programmer card, the MPU, and the appropriate device adapter. The MPU performs continuity checks to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardware Data Sheet. The Altera software can use text- or waveform-format test vectors created with the Altera Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation. Data I/O, BP Microsystems, and other programming hardware manufacturers provide programming support for Altera devices. f IEEE Std. 1149.1 (JTAG) Boundary-Scan Support For more information, see Programming Hardware Manufacturers. MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std. 1149.1. Table 5 describes the JTAG instructions supported by MAX 7000A devices. The pin-out tables, available from the Altera web site (http://www.altera.com), show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins. Altera Corporation 17 MAX 7000A Programmable Logic Device Data Sheet Table 5. MAX 7000A JTAG Instructions JTAG Instruction SAMPLE/PRELOAD EXTEST BYPASS Description Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation Selects the IDCODE register and places it between the TDI and TDO pins, allowing the IDCODE to be serially shifted out of TDO Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE value to be shifted out of TDO. The USERCODE instruction is available for MAX 7000AE devices only These instructions select the user electronic signature (UESCODE) and allow the UESCODE to be shifted out of TDO. UESCODE instructions are available for EPM7128A and EPM7256A devices only. These instructions are used when programming MAX 7000A devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or using a Jam STAPL File, JBC File, or SVF File via an embedded processor or test equipment. IDCODE USERCODE UESCODE ISP Instructions 18 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet The instruction register length of MAX 7000A devices is 10 bits. The user electronic signature (UES) register length in MAX 7000A devices is 16 bits. The MAX 7000AE USERCODE register length is 32 bits. Tables 6 and 7 show the boundary-scan register length and device IDCODE information for MAX 7000A devices. Table 6. MAX 7000A Boundary-Scan Register Length Device EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Boundary-Scan Register Length 96 192 288 288 480 480 624 Table 7. 32-Bit MAX 7000A Device IDCODE Device Version (4 Bits) EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Notes: (1) (2) Note (1) IDCODE (32 Bits) Part Number (16 Bits) 0111 0000 0011 0010 0111 0000 0110 0100 0111 0001 0010 1000 0111 0001 0010 1000 0111 0010 0101 0110 0111 0010 0101 0110 0111 0101 0001 0010 Manufacturer's 1 (1 Bit) Identity (11 Bits) (2) 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 1 1 1 1 1 1 1 0001 0001 0000 0001 0000 0001 0001 The most significant bit (MSB) is on the left. The least significant bit (LSB) for all JTAG IDCODEs is 1. f See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG BST. Altera Corporation 19 MAX 7000A Programmable Logic Device Data Sheet Figure 8 shows timing information for the JTAG signals. Figure 8. MAX 7000A JTAG Waveforms TMS TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH tJSZX tJSCO tJSXZ Table 8 shows the JTAG timing parameters and values for MAX 7000A devices. Table 8. JTAG Timing Parameters & Values for MAX 7000A Devices Note (1) Symbol tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ Note: (1) Timing parameters shown in this table apply for all specified VCCIO levels. Parameter TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance Min 100 50 50 20 45 Max Unit ns ns ns ns ns 25 25 25 20 45 25 25 25 ns ns ns ns ns ns ns ns 20 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Programmable Speed/Power Control MAX 7000A devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more because most logic applications require only a small fraction of all gates to operate at maximum frequency. The designer can program each individual macrocell in a MAX 7000A device for either high-speed (i.e., with the Turbo BitTM option turned on) or low-power operation (i.e., with the Turbo Bit option turned off). As a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters. Output Configuration MAX 7000A device outputs can be programmed to meet a variety of system-level requirements. MultiVolt I/O Interface The MAX 7000A device architecture supports the MultiVolt I/O interface feature, which allows MAX 7000A devices to connect to systems with differing supply voltages. MAX 7000A devices in all packages can be set for 2.5-V, 3.3-V, or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). The VCCIO pins can be connected to either a 3.3-V or 2.5-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 2.5-V power supply, the output levels are compatible with 2.5-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels lower than 3.0 V incur a slightly greater timing delay of tOD2 instead of tOD1. Inputs can always be driven by 2.5-V, 3.3-V, or 5.0-V signals. Table 9 describes the MAX 7000A MultiVolt I/O support. Table 9. MAX 7000A MultiVolt I/O Support VCCIO Voltage 2.5 2.5 3.3 Input Signal (V) 3.3 v v 5.0 v v v v Output Signal (V) 2.5 v v v 3.3 5.0 Altera Corporation 21 MAX 7000A Programmable Logic Device Data Sheet Open-Drain Output Option MAX 7000A devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. This output can also provide an additional wired-OR plane. Open-drain output pins on MAX 7000A devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high VIH . When the open-drain pin is active, it will drive low. When the pin is inactive, the resistor will pull up the trace to 5.0 V to meet CMOS VOH requirements. The open-drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The IOL current specification should be considered when selecting a pull-up resistor. Programmable Ground Pins Each unused I/O pin on MAX 7000A devices may be used as an additional ground pin. In EPM7128A and EPM7256A devices, utilizing unused I/O pins as additional ground pins requires using the associated macrocell. In MAX 7000AE devices, this programmable ground feature does not require the use of the associated macrocell; therefore, the buried macrocell is still available for user logic. Slew-Rate Control The output buffer for each MAX 7000A I/O pin has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. When the configuration cell is turned off, the slew rate is set for low-noise performance. Each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling edges of the output signal. 22 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Power Sequencing & Hot-Socketing Because MAX 7000A devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. The VCCIO and VCCINT power planes can be powered in any order. Signals can be driven into MAX 7000AE devices before and during powerup (and power-down) without damaging the device. Additionally, MAX 7000AE devices do not drive out during power-up. Once operating conditions are reached, MAX 7000AE devices operate as specified by the user. Design Security All MAX 7000A devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. MAX 7000A devices are fully tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 9. Test patterns can be used and then erased during early stages of the production flow. Figure 9. MAX 7000A AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast-groundcurrent transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in brackets are for 2.5-V outputs. Numbers without brackets are for 3.3-V outputs. VCC 703 [521 ] Device Output Generic Testing To Test System 586 [481 ] Device input rise and fall times < 2 ns C1 (includes jig capacitance) Altera Corporation 23 MAX 7000A Programmable Logic Device Data Sheet Operating Conditions Tables 10 through 13 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for MAX 7000A devices. Note (1) Min -0.5 -2.0 -25 No bias Under bias BGA, FineLine BGA, PQFP, and TQFP packages, under bias -65 -65 Table 10. MAX 7000A Device Absolute Maximum Ratings Symbol VCC VI IOUT TSTG TA TJ Parameter Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature Conditions With respect to ground (2) Max 4.6 5.75 25 150 135 135 Unit V V mA C C C Table 11. MAX 7000A Device Recommended Operating Conditions Symbol VCCINT VCCIO Parameter Supply voltage for internal logic (3), (13) and input buffers Supply voltage for output drivers, 3.3-V operation Supply voltage for output drivers, 2.5-V operation (3) (3) Conditions Min 3.0 3.0 2.3 3.0 Max 3.6 3.6 2.7 3.6 5.75 VCCIO 70 85 125 90 105 130 40 40 Unit V V V V V V C C C C C C ns ns VCCISP VI VO TA Supply voltage during insystem programming Input voltage Output voltage Ambient temperature Commercial range Industrial range (5) Extended range (5) (4) -0.5 0 0 -40 -40 0 -40 -40 TJ Junction temperature Commercial range Industrial range (5) Extended range (5) tR tF Input rise time Input fall time 24 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 12. MAX 7000A Device DC Operating Conditions Symbol VIH VIL VOH Note (6) Min 1.7 -0.5 Parameter High-level input voltage Low-level input voltage 3.3-V high-level TTL output voltage Conditions Max 5.75 0.8 Unit V V V V V V V IOH = -8 mA DC, VCCIO = 3.00 V (7) 2.4 VCCIO - 0.2 2.1 2.0 1.7 0.45 0.2 0.2 0.4 0.7 -10 -10 20 30 20 10 10 50 80 74 3.3-V high-level CMOS output IOH = -0.1 mA DC, VCCIO = 3.00 V (7) voltage 2.5-V high-level output voltage IOH = -100 A DC, VCCIO = 2.30 V (7) IOH = -1 mA DC, VCCIO = 2.30 V (7) IOH = -2 mA DC, VCCIO = 2.30 V (7) VOL 3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage 2.5-V low-level output voltage IOL = 8 mA DC, VCCIO = 3.00 V (8) IOL = 0.1 mA DC, VCCIO = 3.00 V (8) IOL = 100 A DC, VCCIO = 2.30 V (8) IOL = 1 mA DC, VCCIO = 2.30 V (8) IOL = 2 mA DC, VCCIO = 2.30 V (8) II IOZ RISP Input leakage current Tri-state output off-state current VI = -0.5 to 5.5 V (9) VI = -0.5 to 5.5 V (9) V V V V V A A k k k Value of I/O pin pull-up resistor VCCIO = 3.0 to 3.6 V (10) during in-system programming VCCIO = 2.3 to 2.7 V (10) or during power-up VCCIO = 2.3 to 3.6 V (11) Table 13. MAX 7000A Device Capacitance Symbol CIN CI/O Note (12) Conditions Min Max 8 8 Parameter Input pin capacitance I/O pin capacitance Unit pF pF VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz Altera Corporation 25 MAX 7000A Programmable Logic Device Data Sheet Notes to tables: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) See the Operating Requirements for Altera Devices Data Sheet. Minimum DC input voltage is -0.5 V. During transitions, the inputs may undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns. For EPM7128A and EPM7256A devices only, VCC must rise monotonically. In MAX 7000AE devices, all pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before VCCINT and VCCIO are powered. These devices support in-system programming for -40 to 100 C. For in-system programming support between -40 and 0 C, contact Altera Applications. These values are specified under the recommended operating conditions shown in Table 11 on page 24. The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers to high-level TTL or CMOS output current. The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to low-level TTL or CMOS output current. This value is specified for normal device operation. For MAX 7000AE devices, the maximum leakage current during power-up is 300 A. For EPM7128A and EPM7256A devices, leakage current during power-up is not specified. For EPM7128A and EPM7256A devices, this pull-up exists while a device is programmed in-system. For MAX 7000AE devices, this pull-up exists while devices are programmed in-system and in unprogrammed devices during power-up. Capacitance is measured at 25 C and is sample-tested only. The OE1 pin (high-voltage pin during programming) has a maximum capacitance of 20 pF. The POR time for MAX 7000AE devices (except MAX 7128A and MAX 7256A devices) does not exceed 100 s. The sufficient V CCINT voltage level for POR is 3.0 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level. 26 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 10 shows the typical output drive characteristics of MAX 7000A devices. Figure 10. Output Drive Characteristics of MAX 7000A Devices 3.3 V 150 MAX 7000AE Devices 2.5 V 150 MAX 7000AE Devices IOL IOL 100 Typical I O Output Current (mA) 50 VCCINT = 3.3 V VCCIO = 3.3 V O Temperature = 25 C Typical I O Output Current (mA) 100 VCCINT = 3.3 V VCCIO = 2.5 V O Temperature = 25 C 50 IOH 0 0 IOH 4 5 0 0 1 2 3 1 2 3 4 5 VO Output Voltage (V) VO Output Voltage (V) 3.3 V 120 EPM7128A & EPM7256A Devices 2.5 V 120 EPM7128A & EPM7256A Devices I OL I OL 80 Typical I O Output Current (mA) 40 Typical I O VCCINT = 3.3 V Output VCCIO = 3.3 V O Temperature = 25 C Current (mA) 80 VCCINT = 3.3 V VCCIO = 2.5 V O Temperature = 25 C 40 IOH 0 0 IOH 4 5 0 1 2 3 1 2 3 4 5 VO Output Voltage (V) VO Output Voltage (V) Timing Model MAX 7000A device timing can be analyzed with the Altera software, a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 11. MAX 7000A devices have predictable internal delays that enable the designer to determine the worst-case timing of any design. The software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation. Altera Corporation 27 MAX 7000A Programmable Logic Device Data Sheet Figure 11. MAX 7000A Timing Model Internal Output Enable Delay t IOE Input Delay t IN PIA Delay t PIA Global Control Delay t GLOB Logic Array Delay t LAD Register Control Delay t LAC tIC t EN Shared Expander Delay t SEXP Fast Input Delay tFIN Parallel Expander Delay t PEXP Register Delay t SU tH t PRE t CLR t RD t COMB t FSU t FH Output Delay t OD1 t OD2 t OD3 t XZ t Z X1 t Z X2 t Z X3 I/O Delay tIO The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. Figure 12 shows the timing relationship between internal and external delay parameters. f See Application Note 94 (Understanding MAX 7000 Timing) for more information. 28 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 12. MAX 7000A Switching Waveforms tR & tF < 2 ns. Inputs are driven at 3 V for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Combinatorial Mode tIN Input Pin tIO I/O Pin tPIA PIA Delay tSEXP Shared Expander Delay tLAC , tLAD Logic Array Input tPEXP Parallel Expander Delay tCOMB Logic Array Output tOD Output Pin Global Clock Mode Global Clock Pin Global Clock at Register tR tIN tCH tGLOB tH tCL tF tSU Data or Enable (Logic Array Output) Array Clock Mode tR Input or I/O Pin tACH tIN tIO tACL tF Clock into PIA Clock into Logic Array Clock at Register Data from Logic Array tPIA tIC tSU tH tRD Register to PIA to Logic Array tPIA tOD tCLR , tPRE tOD tPIA Register Output to Pin Altera Corporation 29 MAX 7000A Programmable Logic Device Data Sheet Tables 14 through 27 show EPM7032AE, EPM7064AE, EPM7128AE, EPM7256AE, EPM7512AE, EPM7128A, and EPM7256A timing information. Table 14. EPM7032AE External Timing Parameters Symbol Parameter Conditions -4 Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay C1 = 35 pF Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock period Maximum internal global clock frequency Maximum internal array clock frequency (3) (2) (2), (4) 227.3 4.4 227.3 138.9 (2) (2) C1 = 35 pF (2) C1 = 35 pF (2) C1 = 35 pF (2) (2) (2) 2.9 0.0 2.5 0.0 1.0 2.0 2.0 1.6 0.3 1.0 2.0 2.0 2.0 4.4 138.9 7.2 103.1 4.3 3.0 Note (1) Speed Grade -7 Max 4.5 4.5 4.7 0.0 3.0 0.0 1.0 3.0 3.0 2.5 0.5 1.0 3.0 3.0 3.0 7.2 103.1 9.7 7.2 5.0 Unit -10 Min Max 7.5 7.5 Min Max 10 10 ns ns ns ns ns ns 6.7 ns ns ns ns ns 9.4 ns ns ns ns 9.7 ns MHz ns MHz 6.3 0.0 3.0 0.0 1.0 4.0 4.0 3.6 0.5 1.0 4.0 4.0 4.0 Minimum array clock period (2) (2), (4) 30 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 15. EPM7032AE Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -4 Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Note (1) Speed Grade -7 -10 Max 1.2 1.2 2.8 3.1 0.8 2.5 1.0 0.0 1.3 Unit Max 0.7 0.7 2.3 1.9 0.5 1.5 0.6 0.0 0.8 Min Min Max 1.5 1.5 3.4 4.0 1.0 3.3 1.2 0.0 1.8 ns ns ns ns ns ns ns ns ns tOD2 C1 = 35 pF (5) C1 = 35 pF 1.3 1.8 2.3 ns tOD3 5.8 6.3 6.8 ns tZX1 Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF (5) slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay 1.3 0.6 1.0 1.5 4.0 4.0 5.0 ns tZX2 4.5 4.5 5.5 ns tZX3 9.0 9.0 10.0 ns tXZ tSU tH tFSU tFH tRD tCOMB 4.0 2.0 1.0 1.5 1.5 0.7 0.6 4.0 2.8 1.3 1.5 1.5 1.2 1.0 5.0 ns ns ns ns ns 1.5 1.3 ns ns Altera Corporation 31 MAX 7000A Programmable Logic Device Data Sheet Table 15. EPM7032AE Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -4 Min tIC tEN tGLOB tPRE tCLR tPIA tLPA Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (6) Note (1) Speed Grade -7 -10 Max 2.0 1.0 1.3 1.9 1.9 1.5 4.0 Unit Max 1.2 0.6 0.8 1.2 1.2 0.9 2.5 Min Min Max 2.5 1.2 1.9 2.6 2.6 2.1 5.0 ns ns ns ns ns ns ns 32 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 16. EPM7064AE External Timing Parameters Symbol Parameter Conditions -4 Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to nonregistered output I/O input to nonregistered output Global clock setup time Global clock setup time of fast input Global clock hold time of fast input Global clock to output C1 = 35 pF delay Global clock high time Global clock low time Array clock setup time (2) Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset (3) (2) C1 = 35 pF (2) C1 = 35 pF (2) C1 = 35 pF (2) (2) 2.8 0.0 2.5 0.0 1.0 2.0 2.0 1.6 0.3 1.0 2.0 2.0 2.0 Note (1) Speed Grade -7 Max 4.5 4.5 4.7 0.0 3.0 0.0 3.1 1.0 3.0 3.0 2.6 0.4 4.3 1.0 3.0 3.0 3.0 4.5 7.4 135.1 4.5 7.4 135.1 100.0 100.0 10.0 7.2 5.1 Unit -10 Min Max 7.5 7.5 Min Max 10.0 10.0 ns ns ns ns ns ns 7.0 ns ns ns ns ns 9.6 ns ns ns ns 10.0 ns MHz ns MHz 6.2 0.0 3.0 0.0 1.0 4.0 4.0 3.6 0.6 1.0 4.0 4.0 4.0 Global clock hold time (2) Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) 222.2 222.2 Maximum internal (2), (4) array clock frequency Altera Corporation 33 MAX 7000A Programmable Logic Device Data Sheet Table 17. EPM7064AE Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -4 Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Note (1) Speed Grade -7 -10 Max 1.1 1.1 3.0 3.0 0.7 2.5 1.0 0.0 1.3 Unit Max 0.6 0.6 2.5 1.8 0.4 1.5 0.6 0.0 0.8 Min Min Max 1.4 1.4 3.7 3.9 0.9 3.2 1.2 0.0 1.8 ns ns ns ns ns ns ns ns ns tOD2 C1 = 35 pF (5) C1 = 35 pF 1.3 1.8 2.3 ns tOD3 5.8 6.3 6.8 ns tZX1 Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF (5) slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay 1.3 0.6 1.0 1.5 4.0 4.0 5.0 ns tZX2 4.5 4.5 5.5 ns tZX3 9.0 9.0 10.0 ns tXZ tSU tH tFSU tFH tRD tCOMB 4.0 2.0 1.0 1.5 1.5 0.7 0.6 4.0 2.9 1.3 1.5 1.5 1.2 0.9 5.0 ns ns ns ns ns 1.6 1.3 ns ns 34 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 17. EPM7064AE Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -4 Min tIC tEN tGLOB tPRE tCLR tPIA tLPA Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (6) Note (1) Speed Grade -7 -10 Max 1.9 1.0 1.5 2.1 2.1 1.7 4.0 Unit Max 1.2 0.6 1.0 1.3 1.3 1.0 3.5 Min Min Max 2.5 1.2 2.2 2.9 2.9 2.3 5.0 ns ns ns ns ns ns ns Altera Corporation 35 MAX 7000A Programmable Logic Device Data Sheet Table 18. EPM7128AE External Timing Parameters Symbol Parameter Conditions -5 Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to nonregistered output I/O input to nonregistered output Global clock setup time Global clock setup time of fast input Global clock hold time of fast input Global clock to output C1 = 35 pF delay Global clock high time Global clock low time Array clock setup time (2) Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset (3) (2) C1 = 35 pF (2) C1 = 35 pF (2) C1 = 35 pF (2) (2) 3.3 0.0 2.5 0.0 1.0 2.0 2.0 1.8 0.2 1.0 2.0 2.0 2.0 Note (1) Speed Grade -7 Max 5.0 5.0 4.9 0.0 3.0 0.0 3.4 1.0 3.0 3.0 2.8 0.3 4.9 1.0 3.0 3.0 3.0 5.2 7.7 129.9 5.2 7.7 129.9 98.0 98.0 10.2 7.1 5.0 Unit -10 Min Max 7.5 7.5 Min Max 10 10 ns ns ns ns ns ns 6.6 ns ns ns ns ns 9.4 ns ns ns ns 10.2 ns MHz ns MHz 6.6 0.0 3.0 0.0 1.0 4.0 4.0 3.8 0.4 1.0 4.0 4.0 4.0 Global clock hold time (2) Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) 192.3 192.3 Maximum internal (2), (4) array clock frequency 36 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 19. EPM7128AE Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -5 Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Note (1) Speed Grade -7 -10 Max 1.0 1.0 3.0 2.9 0.7 2.4 1.0 0.0 1.2 Unit Max 0.7 0.7 2.5 2.0 0.4 1.6 0.7 0.0 0.8 Min Min Max 1.4 1.4 3.4 3.8 0.9 3.1 1.3 0.0 1.6 ns ns ns ns ns ns ns ns ns tOD2 C1 = 35 pF (5) C1 = 35 pF 1.3 1.7 2.1 ns tOD3 5.8 6.2 6.6 ns tZX1 Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF (5) slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay 1.4 0.6 1.1 1.4 4.0 4.0 5.0 ns tZX2 4.5 4.5 5.5 ns tZX3 9.0 9.0 10.0 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC 4.0 2.1 1.0 1.6 1.4 0.8 0.5 1.2 4.0 2.9 1.3 1.6 1.4 1.2 0.9 1.7 5.0 ns ns ns ns ns 1.6 1.3 2.2 ns ns ns 37 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 19. EPM7128AE Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -5 Min tEN tGLOB tPRE tCLR tPIA tLPA Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (6) Note (1) Speed Grade -7 -10 Max 1.0 1.6 2.0 2.0 2.0 4.0 Unit Max 0.7 1.1 1.4 1.4 1.4 4.0 Min Min Max 1.3 2.0 2.7 2.7 2.6 5.0 ns ns ns ns ns ns 38 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 20. EPM7256AE External Timing Parameters Symbol Parameter Conditions -5 Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to nonregistered output I/O input to nonregistered output Global clock setup time Global clock setup time of fast input Global clock hold time of fast input Global clock to output C1 = 35 pF delay Global clock high time Global clock low time Array clock setup time (2) Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset (3) (2) C1 = 35 pF (2) C1 = 35 pF (2) C1 = 35 pF (2) (2) 3.9 0.0 2.5 0.0 1.0 2.0 2.0 2.0 0.2 1.0 2.0 2.0 2.0 Note (1) Speed Grade -7 Max 5.5 5.5 5.2 0.0 3.0 0.0 3.5 1.0 3.0 3.0 2.7 0.3 5.4 1.0 3.0 3.0 3.0 5.8 7.9 126.6 5.8 7.9 126.6 95.2 95.2 10.5 7.3 4.8 Unit -10 Min Max 7.5 7.5 Min Max 10 10 ns ns ns ns ns ns 6.4 ns ns ns ns ns 9.7 ns ns ns ns 10.5 ns MHz ns MHz 6.9 0.0 3.0 0.0 1.0 4.0 4.0 3.6 0.5 1.0 4.0 4.0 4.0 Global clock hold time (2) Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) 172.4 172.4 Maximum internal (2), (4) array clock frequency Altera Corporation 39 MAX 7000A Programmable Logic Device Data Sheet Table 21. EPM7256AE Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -5 Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Note (1) Speed Grade -7 -10 Max 0.9 0.9 2.9 2.8 0.5 2.2 1.0 0.0 1.2 Unit Max 0.7 0.7 2.4 2.1 0.3 1.7 0.8 0.0 0.9 Min Min Max 1.2 1.2 3.4 3.7 0.6 2.8 1.3 0.0 1.6 ns ns ns ns ns ns ns ns ns tOD2 C1 = 35 pF (5) C1 = 35 pF 1.4 1.7 2.1 ns tOD3 5.9 6.2 6.6 ns tZX1 Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF (5) slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay 1.5 0.7 1.1 1.4 4.0 4.0 5.0 ns tZX2 4.5 4.5 5.5 ns tZX3 9.0 9.0 10.0 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC 40 4.0 2.1 0.9 1.6 1.4 0.9 0.5 1.2 4.0 2.9 1.2 1.6 1.4 1.2 0.8 1.6 5.0 ns ns ns ns ns 1.6 1.2 2.1 ns ns ns Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 21. EPM7256AE Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -5 Min tEN tGLOB tPRE tCLR tPIA tLPA Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (6) Note (1) Speed Grade -7 -10 Max 1.0 1.5 2.3 2.3 2.4 4.0 Unit Max 0.8 1.0 1.6 1.6 1.7 4.0 Min Min Max 1.3 2.0 3.0 3.0 3.2 5.0 ns ns ns ns ns ns Altera Corporation 41 MAX 7000A Programmable Logic Device Data Sheet Table 22. EPM7512AE External Timing Parameters Symbol Parameter Conditions -7 Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to nonregistered output I/O input to nonregistered output Global clock setup time Global clock setup time of fast input Global clock hold time of fast input Global clock to output C1 = 35 pF delay Global clock high time Global clock low time Array clock setup time (2) Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset (3) (2) C1 = 35 pF (2) C1 = 35 pF (2) C1 = 35 pF (2) (2) 5.6 0.0 3.0 0.0 1.0 3.0 3.0 2.5 0.2 1.0 3.0 3.0 3.0 Note (1) Speed Grade -10 Max 7.5 7.5 7.6 0.0 3.0 0.0 4.7 1.0 4.0 4.0 3.5 0.3 7.8 1.0 4.0 4.0 4.0 8.6 11.5 87.0 8.6 11.5 87.0 71.9 71.9 13.9 10.4 6.3 Unit -12 Min Max 10.0 10.0 Min Max 12.0 12.0 ns ns ns ns ns ns 7.5 ns ns ns ns ns 12.5 ns ns ns ns 13.9 ns MHz ns MHz 9.1 0.0 3.0 0.0 1.0 5.0 5.0 4.1 0.4 1.0 5.0 5.0 5.0 Global clock hold time (2) Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) 116.3 116.3 Maximum internal (2), (4) array clock frequency 42 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 23. EPM7512AE Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -7 Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Note (1) Speed Grade -10 -12 Max 0.9 0.9 3.6 3.5 0.5 2.8 1.3 0.0 1.5 Unit Max 0.7 0.7 3.1 2.7 0.4 2.2 1.0 0.0 1.0 Min Min Max 1.0 1.0 4.1 4.4 0.6 3.5 1.7 0.0 1.7 ns ns ns ns ns ns ns ns ns tOD2 C1 = 35 pF (5) C1 = 35 pF 1.5 2.0 2.2 ns tOD3 6.0 6.5 6.7 ns tZX1 Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF (5) slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay 2.1 0.6 1.6 1.4 4.0 5.0 5.0 ns tZX2 4.5 5.5 5.5 ns tZX3 9.0 10.0 10.0 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC 4.0 3.0 0.8 1.6 1.4 1.3 0.6 1.8 5.0 3.5 1.0 1.6 1.4 1.7 0.8 2.3 5.0 ns ns ns ns ns 2.1 1.0 2.9 ns ns ns 43 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 23. EPM7512AE Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -7 Min tEN tGLOB tPRE tCLR tPIA tLPA Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (6) Note (1) Speed Grade -10 -12 Max 1.3 2.2 1.4 1.4 4.0 5.0 Unit Max 1.0 1.7 1.0 1.0 3.0 4.5 Min Min Max 1.7 2.7 1.7 1.7 4.8 5.0 ns ns ns ns ns ns 44 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 24. EPM7128A External Timing Parameters Symbol Parameter Conditions -6 Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to non-registered output I/O input to nonregistered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for (3) clear and preset Minimum global clock period (2) 144.9 (2) (2) C1 = 35 pF (2) C1 = 35 pF C1 = 35 pF (2) C1 = 35 pF (2) (2) (2) 4.2 0.0 2.5 0.0 1.0 3.0 3.0 1.9 1.5 1.0 3.0 3.0 3.0 Note (1) Speed Grade -7 Max 6.0 6.0 5.3 0.0 3.0 0.0 3.7 1.0 3.0 3.0 2.4 2.2 6.0 1.0 3.0 3.0 3.0 6.9 116.3 6.9 8.6 116.3 87 8.6 87.0 11.5 72.5 7.5 4.6 Unit -12 Min Max 12.0 12.0 8.5 0.0 3.0 0.0 6.1 1.0 5.0 5.0 3.8 4.3 10.0 1.0 5.0 5.0 5.0 11.5 72.5 13.8 13.8 12.0 7.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz -10 Max 7.5 7.5 7.0 0.0 3.0 0.0 1.0 4.0 4.0 3.1 3.3 1.0 4.0 4.0 4.0 Min Min Max 10.0 10.0 Maximum internal global (2), (4) clock frequency Minimum array clock period Maximum internal array clock frequency (2) (2), (4) 144.9 Altera Corporation 45 MAX 7000A Programmable Logic Device Data Sheet Table 25. EPM7128A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -6 Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay C1 = 35 pF Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V C1 = 35 pF Output buffer and pad delay, slow slew rate = off (5) VCCIO = 2.5 V C1 = 35 pF Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Output buffer enable delay, slow slew rate = off VCCIO = 3.3 V C1 = 35 pF Output buffer enable delay, slow slew rate = off (5) VCCIO = 2.5 V C1 = 35 pF Output buffer enable delay, slow slew rate = on VCCIO = 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input C1 = 5 pF 1.9 1.5 0.8 1.7 Note (1) Speed Grade -7 -10 Max 0.7 0.7 3.1 3.2 0.8 3.0 3.0 0.0 0.6 Unit -12 Min Max 1.1 1.1 3.9 5.1 1.3 4.9 4.9 0.0 0.9 ns ns ns ns ns ns ns ns ns Max 0.6 0.6 2.7 2.5 0.7 2.4 2.4 0.0 0.4 Min Min Max 0.9 0.9 3.6 4.3 1.1 4.1 4.1 0.0 0.7 tOD2 0.9 1.1 1.2 1.4 ns tOD3 5.4 5.6 5.7 5.9 ns tZX1 4.0 4.0 5.0 5.0 ns tZX2 4.5 4.5 5.5 5.5 ns tZX3 9.0 9.0 10.0 10.0 ns tXZ tSU tH tFSU tFH 4.0 2.4 2.2 1.1 1.9 4.0 3.1 3.3 1.1 1.9 5.0 3.8 4.3 1.1 1.9 5.0 ns ns ns ns ns 46 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 25. EPM7128A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -6 Min tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (6) Note (1) Speed Grade -7 -10 Max 2.1 2.1 3.0 3.0 1.2 3.9 3.9 1.1 10.0 Unit -12 Min Max 3.3 3.3 4.9 4.9 2.0 6.2 6.2 1.8 10.0 ns ns ns ns ns ns ns ns ns Max 1.7 1.7 2.4 2.4 1.0 3.1 3.1 0.9 11.0 Min Min Max 2.8 2.8 4.1 4.1 1.7 5.2 5.2 1.5 10.0 Altera Corporation 47 MAX 7000A Programmable Logic Device Data Sheet Table 26. EPM7256A External Timing Parameters Symbol Parameter Conditions -6 Min tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to non-registered output I/O input to nonregistered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for (3) clear and preset Minimum global clock period (2) 156.3 (2) (2) C1 = 35 pF (2) C1 = 35 pF C1 = 35 pF (2) C1 = 35 pF (2) (2) (2) 3.7 0.0 2.5 0.0 1.0 3.0 3.0 0.8 1.9 1.0 3.0 3.0 3.0 Note (1) Speed Grade -7 Max 6.0 6.0 4.6 0.0 3.0 0.0 3.3 1.0 3.0 3.0 1.0 2.7 6.2 1.0 3.0 3.0 3.0 6.4 125.0 6.4 8.0 125.0 93.5 8.0 93.5 10.7 78.1 7.8 4.2 Unit -12 Min Max 12.0 12.0 7.4 0.0 3.0 0.0 5.5 1.0 4.0 4.0 1.6 5.1 10.3 1.0 4.0 4.0 4.0 10.7 78.1 12.8 12.8 12.4 6.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz -10 Max 7.5 7.5 6.2 0.0 3.0 0.0 1.0 4.0 4.0 1.4 4.0 1.0 4.0 4.0 4.0 Min Min Max 10.0 10.0 Maximum internal global (2), (4) clock frequency Minimum array clock period Maximum internal array clock frequency (2) (2), (4) 156.3 48 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Table 27. EPM7256A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions -6 Min tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Fast input delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay C1 = 35 pF Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V C1 = 35 pF Output buffer and pad delay, slow slew rate = off (5) VCCIO = 2.5 V C1 = 35 pF Output buffer and pad delay slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF Output buffer enable delay slow slew rate = off VCCIO = 3.3 V C1 = 35 pF Output buffer enable delay slow slew rate = off (5) VCCIO = 2.5 V C1 = 35 pF Output buffer enable delay slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input C1 = 5 pF 1.0 1.7 1.2 1.3 Note (1) Speed Grade -7 -10 Max 0.4 0.4 3.0 3.5 0.6 3.1 3.1 0.3 0.4 Unit -12 Min Max 0.6 0.6 3.8 5.6 1.0 5.0 5.0 0.5 0.6 ns ns ns ns ns ns ns ns ns Max 0.3 0.3 2.4 2.8 0.5 2.5 2.5 0.2 0.3 Min Min Max 0.5 0.5 3.4 4.7 0.8 4.2 4.2 0.4 0.5 tOD2 0.8 0.9 1.0 1.1 ns tOD3 5.3 5.4 5.5 5.6 ns tZX1 4.0 4.0 5.0 5.0 ns tZX2 4.5 4.5 5.5 5.5 ns tZX3 9.0 9.0 10.0 10.0 ns tXZ tSU tH tFSU tFH 4.0 1.3 2.4 1.4 1.6 4.0 1.7 3.7 1.4 1.6 5.0 2.0 4.7 1.4 1.6 5.0 ns ns ns ns ns Altera Corporation 49 MAX 7000A Programmable Logic Device Data Sheet Table 27. EPM7256A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions -6 Min tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA (1) (2) (3) Note (1) Speed Grade -7 -10 Max 2.0 2.0 3.4 3.1 1.4 2.9 2.9 1.6 10.0 Unit -12 Min Max 3.2 3.2 5.4 5.0 2.2 4.6 4.6 2.6 10.0 ns ns ns ns ns ns ns ns ns Max 1.6 1.6 2.7 2.5 1.1 2.3 2.3 Min Min Max 2.7 2.7 4.5 4.2 1.8 3.8 3.8 2.1 10.0 Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Low-power adder (2) (6) 1.3 11.0 Notes to tables: These values are specified under the recommended operating conditions shown in Table 11 on page 24. See Figure 12 for more information on switching waveforms. These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0.1 ns to the PIA timing value. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. This parameter is measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB. Operating conditions: V CCIO = 2.5 0.2 V for commercial and industrial use. The tLPA parameter must be added to the tLAD , tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in low-power mode. (4) (5) (6) Power Consumption Supply power (P) versus frequency (fMAX, in MHz) for MAX 7000A devices is calculated with the following equation: P = PINT + PIO = ICCINT x VCC + PIO The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The ICCINT value depends on the switching frequency and the application logic. The ICCINT value is calculated with the following equation: ICCINT = (A x MCTON) + [B x (MCDEV - MCTON)] + (C x MCUSED x fMAX x togLC) 50 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet The parameters in this equation are: MCTON MCDEV MCUSED fMAX togLC A, B, C = = = = = = Number of macrocells with the Turbo Bit option turned on, as reported in the MAX+PLUS II Report File (.rpt) Number of macrocells in the device Total number of macrocells in the design, as reported in the Report File Highest clock frequency to the device Average percentage of logic cells toggling at each clock (typically 12.5%) Constants, shown in Table 28 Table 28. MAX 7000A ICC Equation Constants Device EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE A 0.71 0.71 0.71 0.71 0.71 0.71 0.71 B 0.30 0.30 0.30 0.30 0.30 0.30 0.30 C 0.014 0.014 0.014 0.014 0.014 0.014 0.014 This calculation provides an ICC estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each LAB with no output load. Actual ICC should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Altera Corporation 51 MAX 7000A Programmable Logic Device Data Sheet Figure 13 shows the typical supply current versus frequency for MAX 7000A devices. Figure 13. ICC vs. Frequency for MAX 7000A Devices (Part 1 of 2) EPM7032AE 40 35 30 25 EPM7064AE 80 VCC = 3.3 V Room Temperature 227.3 MHz 70 60 VCC = 3.3 V Room Temperature 222.2 MHz High Speed Typical ICC Active (mA) 144.9 MHz 50 40 30 High Speed Typical ICC Active (mA) 20 15 10 5 125.0 MHz 20 Low Power 10 Low Power 0 50 100 150 200 250 0 50 100 150 200 250 Frequency (MHz) EPM7128A & EPM7128AE 160 140 120 100 Frequency (MHz) VCC = 3.3 V Room Temperature 192.3 MHz High Speed Typical ICC Active (mA) 80 60 40 108.7 MHz Low Power 20 0 50 100 150 200 250 Frequency (MHz) 52 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 13. ICC vs. Frequency for MAX 7000A Devices (Part 2 of 2) EPM7256A & EPM7256AE 300 EPM7512AE 600 250 VCC = 3.3 V Room Temperature 172.4 MHz 500 VCC = 3.3 V Room Temperature 116.3 MHz 200 400 Typical ICC Active (mA) High Speed 150 Typical ICC Active (mA) High Speed 300 100 102.0 MHz 200 76.3 MHz 50 Low Power 100 Low Power 0 50 100 150 200 0 20 40 60 80 100 120 140 Frequency (MHz) Frequency (MHz) Device Pin-Outs See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Figures 14 through 23 show the package pin-out diagrams for MAX 7000A devices. Figure 14. 44-Pin PLCC/TQFP Package Pin-Out Diagram Package outlines not drawn to scale. INPUT/OE2/GCLK2 INPUT/OE2/GCLK2 INPUT/GCLRn INPUT/GCLRn INPUT/GCLK1 INPUT/OE1n INPUT/GCLK1 INPUT/OE1n GND VCC GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin 1 Pin 34 6 I/O/TDI I/O I/O GND I/O I/O I/O/TMS I/O VCC I/O I/O 7 8 9 10 11 12 13 14 15 16 17 54 3 2 1 44 43 42 41 40 39 38 37 36 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O I/O/TDI I/O I/O GND I/O I/O I/O/TMS I/O VCC I/O I/O I/O I/O/TDO I/O I/O EPM7032AE EPM7064AE 35 34 33 32 31 30 29 EPM7032AE EPM7064AE VCC I/O I/O I/O/TCK I/O GND I/O 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND Pin 12 VCC I/O Pin 23 44-Pin PLCC 44-Pin TQFP Altera Corporation 53 MAX 7000A Programmable Logic Device Data Sheet Figure 15. 49-Pin Ultra FineLine BGA Package Pin-Out Diagram Package outlines not drawn to scale. A1 Ball Pad Corner Indicates location of Ball A1 A B C D E EPM7064AE F G 7 6 5 4 3 2 1 Figure 16. 84-Pin PLCC Package Pin-Out Diagram Package outline not drawn to scale. I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GLCRn INPUT/OE1 INPUT/GCLK1 GND I/O I/O I/O VCCIO I/O I/O I/O I/O VCCIO I/O/TDI I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 EPM7128A EPM7128AE I/O I/O GND I/O/TDO I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O 54 I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O I/O GND I/O I/O I/O I/O I/O VCCIO 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 17. 100-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 76 EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE Pin 26 Pin 51 Figure 18. 100-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates location of Ball A1 A B C D E F EPM7064AE EPM7128A EPM7128AE EPM7256AE G H J K 10 9 8 7 6 5 4 3 2 1 Altera Corporation 55 MAX 7000A Programmable Logic Device Data Sheet Figure 19. 144-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Indicates location of Pin 1 Pin 1 Pin 109 EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Pin 37 Pin 73 Figure 20. 169-Pin Ultra FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates location of Ball A1 A B C D E F EPM7064AE EPM7128A EPM7128AE EPM7256AE G H J K 10 9 8 7 6 5 4 3 2 1 56 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 21. 208-Pin PQFP Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin 157 EPM7256A EPM7256AE EPM7512AE Pin 53 Pin 105 Altera Corporation 57 MAX 7000A Programmable Logic Device Data Sheet Figure 22. 256-Pin BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates Location of Ball A1 EPM7512AE A B C D E F G H J K L M N P R T U V W Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 58 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 23. 256-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. A1 Ball Pad Corner Indicates Location of Ball A1 A B C D E F G H EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE J K L M N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Revision History The information contained in the MAX 7000A Programmable Logic Device Data Sheet version 4.3 supersedes information published in previous versions. Version 4.3 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4.3: Added extended temperature devices to document Updated Table 11. Version 4.2 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4.2: Removed Note (1) from Table 2. Removed Note (4) from Tables 3 and 4. Altera Corporation 59 |
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